View MAX1115EKAT_9014006.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

general description the max1115/max1116 low-power, 8-bit, analog-to-digital converters (adcs) feature an internal track/hold (t/h), voltage reference, v dd monitor, clock, and serial interface. the max1115 is specified from +2.7v to+5.5v, and the max1116 is specified from +4.5v to +5.5v. both parts consume only 175? at 100ksps. the full-scale analog input range is determined by the internal reference of +2.048v (max1115) or +4.096v (max1116). the max1115/max1116 also feature autoshutdown power-down mode which reduces power consumption to <1? when the device is not in use. the 3-wire serial interface directly connects to spi, qspi, and microwire devices without external logic. conversions up to 100ksps are per- formed using an internal clock. the max1115/max1116 are available in an 8-pin sot23 package with a footprint that is just 30% of an 8-pin so. ________________________applications low-power, hand-held portable devicessystem diagnostics battery-powered test equipment receive-signal-strength indicators 4ma to 20ma powered remote data-acquisition systems features ? single supply +2.7v to +3.6v (max1115)+4.5v to +5.5v (max1116) ? input voltage range: 0 to v ref ? internal track/hold; 100khz sampling rate ? internal reference +2.048v (max1115)+4.096v (max1116) ? spi/qspi/microwire-compatible serial interface ? small 8-pin sot23 package ? automatic power-down ? low power 175a at 100ksps 18a at +3v and 10ksps 1a in power-down mode max1115/max1116 single-supply, low-power, serial 8-bit adcs ________________________________________________________________ maxim integrated products 1 1 23 4 8 76 5 sclkdout convst gnd i.c. ch0 v dd max1115max1116 sot23 top view i.c. pin configuration 19-1822; rev 1; 2/02 ordering information part temp range pin- pa ck a g e to p m a rk max1115 eka -40 c to +85 c 8 sot23 aadu max1116 eka -40 c to +85 c 8 sot23 aadv autoshutdown is a trademark of maxim integrated products. spi/qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor, corp. for pricing, delivery, and ordering information, please contact maxim/dallas direct! at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. downloaded from: http:///
max1115/max1116 single-supply, low-power, serial 8-bit adcs 2 _______________________________________________________________________________________ absolute maximum ratings electrical characteristics(v dd = +2.7v to +3.6v (max1115), v dd = +4.5v to +5.5v (max1116), t a = t min to t max , unless otherwise noted.) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd ...........................................................-0.3v to +6.0v ch0 to gnd ...............................................-0.3v to (v dd + 0.3v) digital output to gnd ................................-0.3v to (v dd + 0.3v) digital input to gnd ..............................................-0.3v to +6.0v maximum current into any pin .........................................?0ma continuous power dissipation (t a = +70 c) 8-pin sot23 (derate 8.9mw/ c above +70 c)............714mw operating temperature range max111_eka ..................................................-40 c to + 85 ? junction temperature ......................................................+150 ? storage temperature range .............................-60 c to +150 ? lead temperature (soldering, 10s) .................................+300 ? parameter symbol conditions min typ max units dc accuracy resolution 8 bits relative accuracy inl (note 1) 1 lsb differential nonlinearity dnl 1 lsb offset error 0.5 lsb gain error 5 %fsr gain temperature coefficient 90 ppm/ c v dd /2 sampling error 2 7% dynamic performance (25khz sine-wave input, v in = v ref ( p-p ), f sclk = 5mhz, f sample = 100ksps, r in = 100 ) signal-to-noise plus distortion sinad 48 db total harmonic distortion (up to the 5th harmonic) thd -69 db spurious-free dynamic range sfdr 66 db small-signal bandwidth f -3db 4 mhz analog input input voltage range 0 v ref v input leakage current v ch = 0 or v dd 0.7 10 ? input capacitance c in 18 pf internal reference max1115 2.048 voltage v ref max1116 4.096 v power requirements max1115 2.7 5.5 supply voltage v dd max1116 4.5 5.5 v f sample = 10ksps 14 21 max1115 f sample = 100ksps 135 190 f sample = 10ksps 19 25 max1116 f sample = 100ksps 182 230 supply current (note 2) i dd shutdown 0.8 10 ? downloaded from: http:///
max1115/max1116 single-supply, low-power, serial 8-bit adcs _______________________________________________________________________________________ 3 note 1: relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range and of f- set have been calibrated. note 2: input = 0, with logic input levels of 0 and v dd . parameter symbol conditions min typ max units supply rejection ratio psrr full-scale or zero input 0.5 1 lsb/v digital inputs (cnvst and sclk) input high voltage v ih 2v input low voltage v il 0.8 v input hystersis v hyst 0.2 v input current high i ih 10 ? input current low i il 10 ? input capacitance c in 2p f digital output (dout) output high voltage v oh i source = 2ma v dd - 0.5 v i sink = 2ma 0.4 output low voltage v ol i sink = 4ma 0.8 v three-state leakage current i l 0.01 10 ? three-state output capacitance c out 4p f timing characteristics (figures 6a 6d) cnvst high time t csh 100 ns cnvst low time t csl 100 ns conversion time t conv 7.5 ? serial clock high time t ch 75 ns serial clock low time t cl 75 ns serial clock period t cp 200 ns falling of cnvst to doutactive t csd c load = 100pf, figure 1 100 ns serial clock falling edge todout t cd c load = 100pf 10 100 ns serial clock rising edgeto dout high-z t chz c load = 100pf, figure 2 100 500 ns last s er i al c l ock to n ext c n v s t ( successi ve conver si ons on c h 0) t ccs 50 ns electrical characteristics (continued)(v dd = +2.7v to +3.6v (max1115), v dd = +4.5v to +5.5v (max1116), t a = t min to t max , unless otherwise noted.) downloaded from: http:///
max1115/max1116 single-supply, low-power, serial 8-bit adcs 4 _______________________________________________________________________________________ typical operating characteristics (v dd = +3v (max1115), v dd = +5v (max1116), f scu = 5mhz, f sample = 100ksps, c load = 100pf, t a = +25 c, unless otherwise noted.) -1.0 -0.4-0.6 -0.8 -0.2 0 0.2 0.4 0.6 0.8 1.0 0 100 50 150 200 250 300 integral nonlinearity vs. output code max1115 toc01 output code inl (lsb) -0.2-0.4 -0.6 0 0.2 0.4 0.6 0.8 1.0 0 100 50 150 200 250 300 differential nonlinearity vs. output code max1115 toc02 output code dnl (lsb) -0.8 -1.0 0 0.20.1 0.40.3 0.60.5 0.7 shutdown supply current vs. supply voltage max1115 toc03 supply voltage (v) shutdown current ( a) 2.5 3.5 4.5 5.5 100.0 0 0.01 0.1 1 10 100 supply current vs. conversion rate 1.0 max1115 toc04 conversion (ksps) supply current ( a) 10.0 max1116v dd = +5v max1115v dd = +3v 0 50 100 150 200 2.5 3.5 4.5 5.5 supply current vs. supply voltage max1115 toc05 supply voltage (v) supply current ( a) max1115 max1116 d out = 00000000 v dd = v digital inputs 0 50 100 150 200 -40 -15 10 35 60 85 supply current vs. temperature max1115 toc06 temperature ( c) supply current ( a) d out = 00000000 v dd = v ref = v digital inputs max1115v dd = +3v max1116v dd = +5v 5.0 5.2 5.35.1 5.4 5.5 2.5 3.5 4.5 5.5 conversion time vs. supply voltage max1115 toc07 supply voltage (v) conversion time ( s) max1115 toc08 5.0 5.2 5.35.1 5.4 5.5 -40 -15 10 35 60 85 conversion time vs. temperature temperature ( c) conversion time ( s) v dd = +3v v dd = +5v 0 0.6 0.80.4 0.2 1.21.0 1.4 2.5 4.5 3.5 5.5 gain error vs. supply voltage max1115 toc09 supply voltage (v) gain error (%fsr) max1116v dd = +5v max1115v dd = +3v downloaded from: http:///
max1115/max1116 single-supply, low-power, serial 8-bit adcs _______________________________________________________________________________________ 5 max1115 toc10 -2.0 0 0.5 -1.0 -0.5-1.5 1.51.0 2.0 -40 60 35 10 -15 85 gain error vs. temperature temperature ( c) gain error (%fsr) max1116v dd = +5v max1115v dd = +3v -120 -80 -100 -60 -40 -20 0 0 20k 10k 30k 40k 50k fft plot max1115 toc11 analog input frequency (hz) amplitude (db) f sample = 100khz f in = 25.1khz a in = 0.9xv ref p-p -0.5 0 -0.1 0.1 -0.2-0.3 -0.4 0.30.2 0.4 0.5 2.5 3.0 4.0 5.0 4.5 3.5 5.5 offset error vs. supply voltage max1115 toc12 supply voltage (v) offset error (lsb) max1116v dd = +3v max1115v dd = +3v -0.5 0 -0.1 0.1 -0.2-0.3 -0.4 0.30.2 0.4 0.5 -40 -15 60 35 10 85 offset error vs. temperature max1115 toc13 temperature ( c) offset error (lsb) max1116v dd = +3v max1115v dd = +5v 0 10.5% 7.0%3.5% 17.5% 21.0%14.0% 1.982 2.008 2.086 2.060 2.034 2.112 max1115 reference voltage vs. number of pieces max1115 toc14 reference voltage (v) 0 7.0% 3.5% 14.0% 10.5% 17.5% 3.980 4.020 4.140 4.100 4.060 4.180 max1116 reference voltage vs. number of pieces max1115 toc15 reference voltage (v) 21.0% typical operating characteristics (continued) (v dd = +3v (max1115), v dd = +5v (max1116), f scu = 5mhz, f sample = 100ksps, c load = 100pf, t a = +25 c, unless otherwise noted.) downloaded from: http:///
max1115/max1116 detailed description the max1115/max1116 adcs use a successive-approximation conversion technique and input track/hold (t/h) circuitry to convert an analog signal to an 8-bit digital output. the spi/qspi/microwire- compatible interface directly connects to microproces- sors (?s) without additional circuitry (figure 3). track/hold the input architecture of the adc is illustrated in theequivalent-input circuit shown in figure 4 and is com- posed of the t/h, input multiplexer, input comparator, switched capacitor dac, and auto-zero rail. the acquisition interval begins with the falling edge of cnvst. during the acquisition interval, the analog input (ch0) is connected to the hold capacitor (c hold ). once the acquisition is complete, the t/h switch opensand c hold is connected to gnd, which retains the charge on c hold as a sample of the signal at the ana- log input. sufficiently low source impedance is required to ensurean accurate sample. a source impedance of <1.5k is recommended for accurate sample settling. a 100pfcapacitor at the adc inputs also improves the accuracy of an input sample. conversion process the max1115/max1116 conversion process is internal-ly timed. the total acquisition and conversion process takes <7.5?. once an input sample has been acquired, the comparator s negative input is then con- nected to an auto-zero supply. since the devicerequires only a single supply, the negative input of the comparator is set to equal v dd /2. the capacitive dac restores the positive input to v dd /2 within the limits of 8- bit resolution. this action is equivalent to transferring acharge q in = 16pf ? v in from c hold to the binary- weighted capacitive dac, which forms a digital repre-sentation of the analog-input signal. single-supply, low-power, serial 8-bit adcs 6 _______________________________________________________________________________________ pin description pin name function 1v dd positive supply voltage 2 ch0 analog voltage input 3, 5 i.c. internally connected. connect to ground. 4 gnd ground 6 cnvst convert/start input. cnvst initiates a power-up and starts a conversion on its falling edge. 7 dout serial data output. data is clocked out on the falling edge of sclk. dout goes low at the start of a conversion and presents the msb at the completion of a conversion. dout goes high impedance once data has been fully clocked out. 8 sclk serial clock. used for clocking out data on dout. v dd 3k c load gnd dout c load gnd 3k dout a) v ol to v oh b) high-z to v ol and v oh to v ol v dd 3k c load gnd dout c load gnd 3k dout a) v oh to high-z b) v ol to high-z figure 1. load circuits for enable time figure 2. load circuits for disable time downloaded from: http:///
input voltage range internal protection diodes that clamp the analog inputto v dd and gnd allow the input pin (ch0) to swing from (gnd - 0.3v) to (v dd + 0.3v) without damage. however, for accurate conversions, the inputs must notexceed (v dd + 50mv) or be less than (gnd - 50mv). input bandwidth the adc s input tracking circuitry has a 4mhz small- signal bandwidth, so it is possible to digitize high-speed transient events and measure periodic signals with bandwidths exceeding the adc s sampling rate by using undersampling techniques. anti-alias filtering isrecommended to avoid high-frequency signals being aliased into the frequency band of interest. serial interface the max1115/max1116 have a 3-wire serial interface.the cnvst and sclk inputs are used to control the device, while the three-state dout pin is used to access the conversion results. the serial interface provides connection to microcon- trollers (?s) with spi, qspi, and microwire serial interfaces at clock rates up to 5mhz. the interface sup- ports either an idle high or low sclk format. for spi and qspi, set cpol = cpha = 0 or cpol = cpha = 1 in the spi control registers of the ?. figure 5 shows the max1115/max1116 common serial-interface con- nections. see figures 6a 6d for details on the serial- interface timing and protocol. max1115/max1116 single-supply, low-power, serial 8-bit adcs _______________________________________________________________________________________ 7 v dd i/o sck (sk) miso (si) gnd dout sclk convst gnd v dd 0.1 f 1 f ch0 analog inputs max1115max1116 cpu v dd figure 3. typical operating circuit gnd c hold capacitive dac v dd 2 comparator 16pf r in 6.5k auto-zero rail track hold ch0 figure 4. equivalent input circuit convstsclk dout i/o sck miso ss a) spi convstconvst sclkdout cs sck miso +3v ss b) qspi max1115max1116 max1115max1116 max1115max1116 sclkdout i/o sk si c) microwire +3v figure 5. common serial-interface connections downloaded from: http:///
max1115/max1116 digital inputs and outputs the max1115/max1116 perform conversions by usingan internal clock. this frees the ? from the burden of running the sar conversion clock, and allows the con- version results to be read back at the ? s convenience at any clock rate up to 5mhz. the acquisition interval begins with the falling edge ofcnvst. cnvst can idle between conversions in either a high or low state. if idled in a low state, cnvst must be brought high for at least 50ns, then brought low to initiate a conversion. to select v dd /2 for conversion, the cnvst pin must be brought high and low for a second time (figures 6c and 6d). single-supply, low-power, serial 8-bit adcs 8 _______________________________________________________________________________________ active power-down mode cnvst sclk dout ch0 idle low idle low ch0 t csh t conv t cp t ccs t chz t cl t cd d7 (msb) d6 d5 d4 d3 d2 d1 d0 t csd t ch figure 6a. conversion and interface timing, conversion on ch0 with sclk idle low active power-down mode cnvst sclk dout ch0 idle high idle high ch0 t csh t conv t cp t ccs t chz t cl t cd d7 (msb) d6 d5 d4 d3 d2 d1 d0 t csd t ch figure 6b. conversion and interface timing, conversion on ch0 with sclk idle high downloaded from: http:///
after cnvst is brought low, allow 7.5? for the conver-sion to be completed. while the internal conversion is in progress, dout is low. the msb is present at the dout pin immediately after conversion is completed. the conversion result is clocked out at the dout pin and is coded in straight binary (figure 7). data is clocked out at sclk s falling edge in msb-first format at rates up to 5mhz. once all data bits are clocked out,dout goes high impedance (100ns to 500ns after the rising edge) of the eighth sclk pulse. sclk is ignored during the conversion process. only after a conversion is complete will sclk cause serial data to be output. falling edges on cnvst during an max1115/max1116 single-supply, low-power, serial 8-bit adcs _______________________________________________________________________________________ 9 active power-down mode cnvst sclk dout ch0 idle low idle low ch0 t csh t conv t cp t ccs t csl t chz t cl t cd d7 (msb) d6 d5 d4 d3 d2 d1 d0 t csd t ch v dd 2 v dd 2 figure 6c. conversion and interface timing, conversion on v dd / 2 with sclk idle low active power-down mode cnvst sclk dout ch0 idle high idle high ch0 t csh t conv t cp t ccs t csl t chz t cl t cd d7 (msb) d6 d5 d4 d3 d2 d1 d0 t csd t ch v dd 2 v dd 2 figure 6d. conversion and interface timing, conversion on v dd / 2 with sclk idle high downloaded from: http:///
max1115/max1116 active conversion process interrupt the current conver- sion and cause the input multiplexer to switch to v dd /2. to reinitiate a conversion on ch0, it is necessary to allowfor a conversion to be complete and all of the data to be read out. once a conversion has been completed, the max1115/max1116 goes into autoshutdown mode (typically <1?) until the next conversion is initiated. applications information power-on reset when power is first applied, the max1115/max1116 are in autoshutdown (typically <1?). a conversion can be started by toggling cnvst high to low. powering up the max1115/max1116 with cnvst low does not start a conversion. autoshutdown and supply current requirements the max1115/max1116 are designed to automaticallyshutdown once a conversion is complete, without any external control. an input sample and conversion process typically takes 5? to complete, during which time the supply current to the analog sections of the device are fully on. all analog circuitry is shutdown after a conversion completes, which results in a supply cur- rent of <1? (see shutdown current vs. supply voltage plot in the typical operating characteristics section). the digital conversion result is maintained in a staticregister and is available for access through the serial interface at any time. the power consumption consequence of this architec-ture is dramatic when relatively slow conversion rates are needed. for example, at a conversion rate of 10ksps, the average supply current for the max1115 is 15?, while at 1ksps it drops to 15?. at 0.1ksps it is just 0.3?, or a miniscule 1? of power consumption (see average supply current vs. conversion rate plot in the typical operating characteristics sections). transfer function figure 7 depicts the input/output transfer function.output coding is binary with a +2.048v reference, 1lsb = 8mv(v ref /256). layout, grounding, and bypassing for best performance, board layout should ensure thatdigital and analog signal lines are separated from each other. do not run analog and digital (especially clock) lines parallel to one another or run digital lines under- neath the adc package. figure 8 shows the recommended system-ground con- nections. a single-point analog ground (star-ground point) should be established at the adc ground. connect all analog grounds to the star-ground. the ground-return to the power supply for the star ground should be low impedance and as short as possible for noise-free operation. high-frequency noise in the v dd power supply can affect the comparator in the adc. bypass the supply tothe star ground with a 0.1? capacitor close to the v dd pin of the max1115/max1116. minimize capacitor lead single-supply, low-power, serial 8-bit adcs 10 ______________________________________________________________________________________ output code full-scale transition 1111111111111110 11111101 0000001100000010 00000001 00000000 123 0 fs fs - 1/2 lsb fs = v refin + v in- 1lsb = v refin 256 input voltage (lsb) figure 7. input/output transfer function gnd +3v/+5v system power supplies v dd dgnd v dd in- 1 f 10 0.1 f gnd digital circuitry max1115max1116 figure 8. power-supply connections downloaded from: http:///
lengths for best supply-noise rejection. if the powersupply is noisy, a 0.1? capacitor in conjunction with a 10 series resistor can be connected to form a low- pass filter. chip information transistor count: 2000process: bicmos max1115/max1116 single-supply, low-power, serial 8-bit adcs ______________________________________________________________________________________ 11 input multiplexer sclk cnvst ch0 input track and hold internal reference 2.096v or 4.096v split v dd /2 8-bit sar adc output shift register dout control logic and internal ocsillator max1115max1116 functional diagram downloaded from: http:///
max1115/max1116 single-supply, low-power, serial 8-bit adcs maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 12 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2002 maxim integrated products printed usa is a registered trademark of maxim integrated products. sot23, 8l.eps package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline information, go to www.maxim-ic.com/packages .) downloaded from: http:///

▲Up To Search▲

Price & Availability of MAX1115EKAT

	To Download MAX1115EKAT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .